? semiconductor components industries, llc, 2009 august, 2009 ? rev. 4 1 publication order number: nb6l11m/d nb6l11m 2.5v / 3.3v 1:2 differential cml fanout buffer multi ? level inputs w/ internal termination description the nb6l11m is a differential 1:2 cml fanout buffer. the differential inputs incorporate internal 50 termination resistors that are accessed through the v t pins and will accept lvpecl, lvcmos, lvttl, cml, or lvds logic levels. the v refac pin is an internally generated voltage supply available to this device only. v refac is used as a reference voltage for single ? ended pecl or necl inputs. for all single ? ended input conditions, the unused complementary differential input is connected to v refac as a switching reference voltage. v refac may also rebias capacitor ? coupled inputs. when used, decouple v refac with a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v refac output should be left open. the device is housed in a small 3x3 mm 16 pin qfn package. the nb6l11m is a member of the eclinps max family of high performance clock products. features ? maximum input clock frequency > 4 ghz, typical ? 225 ps typical propagation delay ? 70 ps typical rise and fall times ? 0.5 ps maximum rms clock jitter ? differential cml outputs, 380 mv peak ? to ? peak, typical ? lvpecl operating range: v cc = 2.375 v to 3.63 v with v ee = 0 v ? necl operating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.63 v ? internal input termination resistors, 50 ? vrefac reference output ? functionally compatible with existing 2.5 v / 3.3v lvel, lvep, ep, and sg devices ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices marking diagram* http://onsemi.com qfn ? 16 mn suffix case 485g nb6l 11m alyw a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) 16 1 *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on p age 8 of this data sheet. ordering information figure 1. simplified logic diagram q0 q0 q1 q1 d d vtd vtd v refac
nb6l11m http://onsemi.com 2 v cc v refac v ee v cc v cc v ee v ee v cc q0 q0 q1 q1 vtd d d vtd 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb6l11m exposed pad (ep) figure 2. pin configuration (top view) table 1. pin description pin name i/o description 1 vtd ? internal 50 termination pin for d input. 2 d ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. note 1. internal 50 resistor to termination pin, vtd. 3 d ecl, cml, lvcmos, lvds, lvttl input inverted differential input. note 1. internal 50 resistor to termination pin, vtd . 4 vtd ? internal 50 termination pin for d input. 5 v cc ? positive supply voltage 6 v refac output reference voltage for direct or capacitor coupled inputs 7 v ee ? negative supply voltage 8 v cc ? positive supply voltage 9 q1 cml output inverted differential output. typically terminated with 50 resistor to v cc . 10 q1 cml output noninverted differential output. typically terminated with 50 resistor to v cc . 11 q0 cml output inverted differential output. typically terminated with 50 resistor to v cc . 12 q0 cml output noninverted differential output. typically terminated with 50 resistor to v cc . 13 v cc ? positive supply voltage 14 v ee ? negative supply voltage 15 v ee ? negative supply voltage 16 v cc ? positive supply voltage ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to vee on the pc board. 1. in the dif ferential configuration when the input termination pins (vtd, vtd ) are connected to a common termination voltage or left open, and if no signal is applied on d/d input, then, the device will be susceptible to self ? oscillation. 2. all v cc and v ee pins must be externally connected to a power supply for proper operation.
nb6l11m http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model > 2 kv > 200v moisture sensitivity 16 ? qfn level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count meets or exceeds jedec spec eia/jesd78 ic latchup test for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 4.0 v v ee negative power supply v cc = 0 v ? 4.0 v v io positive input/output voltage negative input/output voltage v ee = 0 v v cc = 0 v ? 0.5 v io v cc + 0.5 +0.5 v io v ee ? 0.5 4.0 ? 4.0 v v v inpp differential input voltage |d ? d | v cc ? v ee v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current (cml output) continuous surge 25 50 ma ma i vrefac vrefac sink/source current 0.5 ma t a operating temperature range 16 qfn ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfmp 500 lfmp qfn ? 16 qfn ? 16 42 35 c/w c/w jc thermal resistance (junction ? to ? case) (note 3) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb6l11m http://onsemi.com 4 table 4. dc characteristics, multi ? level inputs v cc = 2.375 v to 3.63 v, v ee = 0 v, or v cc = 0 v, v ee = ? 2.375 v to ? 3.63 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit power supply current i cc power supply current (inputs and outputs open) 45 60 75 ma cml outputs (notes 4 and 5) v oh output high voltage v cc = 3.3 v v cc = 2.5 v v cc ? 40 3260 2460 v cc ? 10 3290 2490 v cc 3300 2500 mv v ol output low voltage v cc = 3.3v v cc = 2.5v v cc ? 500 2800 2000 v cc ? 400 2900 2100 v cc ? 300 3000 2200 mv differential input driven single ? ended (see figures 4 and 5) (note 6) v th input threshold reference voltage range (note 7) 1125 v cc ? 75 mv v ih single ? ended input high voltage v th + 75 v cc mv v il single ? ended input low voltage v ee v th ? 75 mv v ise single ? ended input voltage amplitude (v ih ? v il ) 150 2800 mv vrefac v refac output reference voltage (v cc 2.5 v) v cc ? 1525 v cc ? 1425 v cc ? 1325 mv differential inputs driven differentially (see figures 6, 7 and 8) (note 8) v ihd differential input high voltage v ee + 1200 v cc mv v ild differential input low voltage v ee v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) v ee + 100 v cc ? v ee mv v cmr input common mode range (differential configuration) (note 9) v ee + 950 v cc ? 50 mv i ih input high current d / d , (vtd/v td open) ? 150 150 ua i il input low current d / d , (vtd/v td open) ? 150 150 ua termination resistors r tin internal input termination resistor 40 50 60 r tout internal output termination resistor 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. cml outputs loaded with 50 to v cc for proper operation. 5. input and output parameters vary 1:1 with v cc . 6. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 7. v th is applied to the complementary input when operating in single ? ended mode. 8. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 9. v cmr min varies 1:1 with v ee , v cmr maximum varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the dif ferential input signal.
nb6l11m http://onsemi.com 5 table 5. ac characteristics v cc = 2.375 v to 3.63 v, v ee = 0 v, or v cc = 0 v, v ee = ? 2.375 v to ? 3.63 v, t a = ? 40 c to +85 c; (note 10) symbol characteristic min typ max unit v outpp output voltage amplitude (@ v inpp(min) f in 3.0ghz (note 15) (see figure 9) f in 3.5 ghz f in 4.0 ghz 230 190 150 380 320 270 mv t pd propagation delay d to q 175 225 325 ps t skew duty cycle skew (note 11) within device skew device to device skew (note 12) 5.0 3.0 15 15 80 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 4.0ghz 40 50 60 % t jitter rms random clock jitter (note 13) f in 4ghz peak ? to ? peak data dependent jitter (note 14) f in 4gb/s 0.2 40 0.5 ps v inpp input voltage swing/sensitivity (differential configuration) (note 15) 150 2800 mv t r t f output rise/fall times @ 0.5 ghz q, q (20% ? 80%) 70 120 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% ? 80%). 11. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 0.5ghz. 12. device to device skew is measured between outputs under identical transition @ 0.5 ghz. 13. additive rms jitter with 50% duty cycle clock signal. 14. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 15. input and output voltage swing is a single ? ended measurement operating in differential mode.
nb6l11m http://onsemi.com 6 figure 3. input structure 50 50 vtd vtd v cc d d r c r c i d v th d v th figure 4. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin v ee v th figure 5. v th diagram d d figure 6. differential inputs driven differentially v ild(max) v ihd(max) v ihd v ild v ihd(min) v il(min) v cmr gnd v id = v ihd ? v ild v cc d d q q t pd t pd v outpp = v oh (q) ? v ol (q) v inpp = v ih (d) ? v il (d) figure 7. differential inputs driven differentially figure 8. v cmr diagram figure 9. ac reference measurement v ihd v ild v id = |v ihd(d) ? v ild(d)| d d
nb6l11m http://onsemi.com 7 lvpecl driver v cc v ee z o = 50 v th = v cc ? 2 v z o = 50 nb6l11m d 50 50 d v ee figure 10. lvpecl interface lvds driver v cc gnd z o = 50 z o = 50 nb6l11m 50 * 50 * gnd figure 11. lvds interface v cc v cc figure 12. standard 50 load cml interface figure 13. capacitor ? coupled differential interface (v td /v td connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) figure 14. capacitor ? coupled single ? ended interface (v t /v t connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) v td v td in in v td v td cml driver v cc gnd z o = 50 v t = v t = v cc z o = 50 nb6l11m 50 * 50 * gnd v cc in in v td v td v cc differential driver v cc gnd z o = 50 v th = external v refac z o = 50 nb6l11m 50 * 50 * gnd v cc in in v td v td v th v td v td v th single ? ended driver v cc gnd z o = 50 v th = external v refac nb6l11m 50 * 50 * gnd v cc in in v th
nb6l11m http://onsemi.com 8 800 700 600 500 400 300 200 100 0 0123 f out , clock output frequency (ghz) v outpp output voltage amplitude (mv) (typical) figure 15. output voltage amplitude (v outpp ) versus output frequency at ambient temperature (typical) q q v cc 16 ma 50 50 figure 16. cml output structure v ee 4 driver device receiver device qd figure 17. typical cml termination for output driver and device evaluation q d v cc 50 50 z = 50 z = 50 dut ordering information device package shipping ? nb6l11mmng qfn ? 16 (pb ? free) 123 units / rail NB6L11MMNR2G qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb6l11m http://onsemi.com 9 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 nb6l11m/d the products described herein (nb4l16m), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. eclinps max is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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